Datasheet

Value Description
1
End of linked list condition has occurred since the last read of the Status register.
Bit 0 – BIS End of Block Interrupt Status Bit
Value Description
0
End of block interrupt has not occurred.
1
End of block interrupt has occurred since the last read of the Status register.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 516