Datasheet

36.9.21 XDMAC Channel x Interrupt Status Register [x = 0..23]
Name: XDMAC_CIS
Offset: 0x5C + n*0x40 [n=0..23]
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ROIS WBEIS RBEIS FIS DIS LIS BIS
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bit 6 – ROIS Request Overflow Error Interrupt Status Bit
Value Description
0
Overflow condition has not occurred.
1
Overflow condition has occurred at least once. (This information is only relevant for peripheral
synchronized transfers.)
Bit 5 – WBEIS W
rite Bus Error Interrupt Status Bit
Value Description
0
Write bus error condition has not occurred.
1
At least one bus error has been detected in a write access since the last read of the Status register.
Bit 4 – RBEIS Read Bus Error Interrupt Status Bit
Value Description
0
Read bus error condition has not occurred.
1
At least one bus error has been detected in a read access since the last read of the Status register.
Bit 3 – FIS End of Flush Interrupt Status Bit
Value Description
0
End of flush condition has not occurred.
1
End of flush condition has occurred since the last read of the Status register.
Bit 2 – DIS End of Disable Interrupt Status Bit
Value Description
0
End of disable condition has not occurred.
1
End of disable condition has occurred since the last read of the Status register.
Bit 1 – LIS End of Linked List Interrupt Status Bit
Value Description
0
End of linked list condition has not occurred.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 515