Datasheet

36.9.18 XDMAC Channel x Interrupt Enable Register [x=0..23]
Name: XDMAC_CIE
Offset: 0x50 + n*0x40 [n=0..23]
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ROIE WBIE RBIE FIE DIE LIE BIE
Access
W W W W W W W
Reset – – – – – – –
Bit 6 – ROIE Request Overflow Error Interrupt Enable Bit
Value Description
0
No effect.
1
Enables request overflow error interrupt.
Bit 5 – WBIE W
rite Bus Error Interrupt Enable Bit
Value Description
0
No effect.
1
Enables write bus error interrupt.
Bit 4 – RBIE Read Bus Error Interrupt Enable Bit
Value Description
0
No effect.
1
Enables read bus error interrupt.
Bit 3 – FIE End of Flush Interrupt Enable Bit
Value Description
0
No effect.
1
Enables end of flush interrupt.
Bit 2 – DIE End of Disable Interrupt Enable Bit
Value Description
0
No effect.
1
Enables end of disable interrupt.
Bit 1 – LIE End of Linked List Interrupt Enable Bit
Value Description
0
No effect.
1
Enables end of linked list interrupt.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 509