Datasheet

36.9.15 XDMAC Global Channel Software Request Register
Name: XDMAC_GSWR
Offset: 0x38
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SWREQ23 SWREQ22 SWREQ21 SWREQ20 SWREQ19 SWREQ18 SWREQ17 SWREQ16
Access
W W W W W W W W
Reset – – – – – – – –
Bit 15 14 13 12 11 10 9 8
SWREQ15 SWREQ14 SWREQ13 SWREQ12 SWREQ11 SWREQ10 SWREQ9 SWREQ8
Access
W W W W W W W W
Reset – – – – – – – –
Bit 7 6 5 4 3 2 1 0
SWREQ7 SWREQ6 SWREQ5 SWREQ4 SWREQ3 SWREQ2 SWREQ1 SWREQ0
Access
W W W W W W W W
Reset – – – – – – – –
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – SWREQ XDMAC Channel x
Software Request
Value Description
0
No effect.
1
Requests a DMA transfer for channel x.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 506