Datasheet

36.9.10 XDMAC Global Channel Status Register
Name: XDMAC_GS
Offset: 0x24
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – ST XDMAC Channel x Status
Value Description
0
This bit indicates that the channel x is disabled.
1
This bit indicates that the channel x is enabled. If a channel disable request is issued, this bit remains
asserted until pending transaction is completed.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 501