Datasheet

36.9.8 XDMAC Global Channel Enable Register
Name: XDMAC_GE
Offset: 0x1C
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
EN23 EN22 EN21 EN20 EN19 EN18 EN17 EN16
Access
W W W W W W W W
Reset – – – – – – – –
Bit 15 14 13 12 11 10 9 8
EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8
Access
W W W W W W W W
Reset – – – – – – – –
Bit 7 6 5 4 3 2 1 0
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
Access
W W W W W W W W
Reset – – – – – – – –
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – EN XDMAC Channel x Enable
Value Description
0
This bit has no effect.
1
Enables channel n. This operation is permitted if the Channel x Status bit (XDMAC_GS.STx) was read
as '0'.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 499