Datasheet

36.9.7 XDMAC Global Interrupt Status Register
Name: XDMAC_GIS
Offset: 0x18
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
IS23 IS22 IS21 IS20 IS19 IS18 IS17 IS16
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 – IS XDMAC Channel x Interrupt
Status
Value Description
0
This bit indicates that either the interrupt source is masked at the channel level or no interrupt is
pending for channel x.
1
This bit indicates that an interrupt is pending for the channel x.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 498