Datasheet

36.9.1 XDMAC Global Type Register
Name: XDMAC_GTYPE
Offset: 0x00
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
NB_REQ[6:0]
Access
R R R R R R R
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FIFO_SZ[10:3]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FIFO_SZ[2:0] NB_CH[4:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 22:16 – NB_REQ[6:0] Number of Peripheral Requests Minus One
Bits 15:5 – FIFO_SZ[10:0] Number of Bytes
Bits 4:0 – NB_CH[4:0]
Number of Channels Minus One
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 492