Datasheet

Note:

The bit SLEEPDEEP is in the Cortex-M7 System Control Register.

2. When considering wakeup time, the time required to start the PLL is not taken into account. Once started, the

device works with the Main RC oscillator. The user has to add the PLL startup time if it is needed in the

system. The wakeup time is defined as the time taken for wakeup until the first instruction is fetched.

3. HCLK = MCK. The user may need to revert back to the previous clock configuration.

4. Depends on MCK frequency.

5. In this mode, the core is supplied and not clocked. Some peripherals can be clocked.

6. Resume from Wait mode if a debug request occurs (CDBGPWRUPREQ is set in the processor).

7. CAN wake-up requires the use of any WKUP0–13 pin.

7.7 Wakeup Sources

Wakeup events allow the device to exit Backup mode. When a wakeup event is detected, the Supply Controller

performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are

not already enabled.

7.8 Fast Startup

The SAM E70/S70/V70/V71 allows the processor to restart in a few microseconds while the processor is in Wait

mode or in Sleep mode. A fast startup can occur upon detection of a low level on any of the following wakeup

sources:

• WKUP0 to WKUP13 pins

• Supply Monitor

• RTC alarm

• RTT alarm

• USBHS interrupt line (WAKEUP)

• Processor debug request (CDBGPWRUPREQ)

• GMAC wake on LAN event

Note: CAN wake-up requires the use of any WKUP0–13 pin.

Note:

The fast restart circuitry is fully asynchronous and provides a fast startup signal to the Power Management Controller.

As soon as the fast startup signal is asserted, the PMC automatically restarts the Main RC oscillator, switches the

Master clock on this clock and re-enables the processor clock.

SAM E70/S70/V70/V71 Family

Power Considerations

echnology Inc.

Datasheet

DS60001527D-page 48