Datasheet

To enter Wait mode, first, select the Main RC oscillator as Main Clock and perform the following steps:
1.
Configure the FLPM field in the PMC_FSMR.
2. Set Flash Wait State at 0.
3. Set HCLK = MCK by configuring MDIV to 0 in the PMC Master Clock register (PMC_MCKR).
4. Set the WAITMODE bit in the PMC Clock Generator Main Oscillator register (CKGR_MOR).
5. Wait for MCKRDY = 1 in the PMC Status register (PMC_SR).
Note: Internal main clock resynchronization cycles are necessary between writing the MOSCRCEN bit and
the entry in Wait mode. Depending on the user application, waiting for MOSCRCEN bit to be cleared is
recommended to ensure that the core will not execute undesired instructions.
7.6.3 Sleep Mode
The purpose of Sleep mode is to optimize power consumption of the device versus response time. In this mode, only
the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application-
dependent.
This mode is entered using the instruction Wait for Interrupt (WFI).
Processor wakeup is triggered by an interrupt if the WFI instruction of the Cortex-M processor is used.
7.6.4 Low-Power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up
sources can be individually configured. The following table provides a summary of the configurations of the low-
power modes.
Table 7-2. Low-power Mode Configuration Summary
Mode SUPC, 32 kHz
Oscillator
,
RTC, RTT
Backup SRAM
(BRAM),
Backup
Registers
(GPBR),
POR
(Backup Area)
Regulator Core
Memory
Peripherals
Mode Entry Configuration Potential
Wakeup
Sources
Core at
Wakeup
PIO State while
in Low-Power
Mode
PIO State at
Wakeup
Wakeup Time
(see Note 2)
Backup Mode ON OFF OFF
(Not powered)
SUPC_CR.VROFF = 1
SLEEPDEEP = 1 (see Note 1)
WKUP0–13 pins
Supply Monitor
RTC alarm
RTT alarm
Reset Previous state
maintained
PIOA, PIOB,
PIOC, PIOD &
PIOE
inputs with
pullups
< 2 ms
Wait Mode w/
Flash in Deep
Power-down
Mode
ON ON Powered
(Not clocked)
PMC_MCKR.MDIV = 0
, CKGR_MOR.WAITMODE =1
, SLEEPDEEP = 0
, PMC_FSMR.LPM = 1
, PMC_FSMR.FLPM = 1 (see Note 1)
WKUP0–13 pins
RTC
RTT
USBHS
Processor debug (see Note 6)
GMAC Wake on LAN event
Wakeup from CAN (see Note
7)
Clocked back
(see Note 3)
Previous state
maintained
Unchanged < 10 μs
Wait Mode w/
Flash in
Standby Mode
ON ON Powered
(Not clocked)
PMC_MCKR.MDIV = 0
, CKGR_MOR.WAITMODE =1
, SLEEPDEEP = 0
, PMC_FSMR.LPM = 1
, PMC_FSMR.FLPM = 0 (see Note 1)
WKUP0–13 pins
RTC
RTT
USBHS
Processor debug (see Note 6)
GMAC Wake on LAN
Wakeup from CAN (see Note
7)
Clocked back
(see Note 3)
Previous state
maintained
Unchanged < 10 μs
Sleep Mode ON ON Powered
(Not clocked) (see
Note 4)
WFI
SLEEPDEEP = 0
PMC_FSMR.LPM = 0 (see Note 1)
Any enabled Interrupt Clocked back Previous state
maintained
Unchanged (see Note 5)
SAM E70/S70/V70/V71 Family
Power Considerations
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 47