Datasheet

This indicates that the linked list is disabled and striding is disabled.
9.
Enable the Block interrupt by writing a ‘1’ to XDMAC_CIEx.BIE, enable the Channel x Interrupt Enable bit by
writing a ‘1’ to XDMAC_GIEx.IEx.
10. Enable channel x by writing a ‘1’ to the XDMAC_GE.ENx. XDMAC_GS.STx is set by hardware.
11. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates
an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the
channel status bit.
36.5.4.3 Master Transfer
1. Read the XDMAC_GS register to choose a free channel.
2. Clear the pending Interrupt Status bit by reading the chosen XDMAC_CISx register.
3. Build a linked list of transfer descriptors in memory. The descriptor view is programmable on a per descriptor
basis. The linked list items structure must be word aligned. MBR_UBC.NDE must be configured to 0 in the last
descriptor to terminate the list.
4. Configure field NDA in the XDMAC Channel x Next Descriptor Address Register (XDMAC_CNDAx) with the
first descriptor address and bit XDMAC_CNDAx.NDAIF with the master interface identifier.
5. Configure the XDMAC_CNDCx register:
5.1. Set XDMAC_CNDCx.NDE to enable the descriptor fetch.
5.2. Set XDMAC_CNDCx.NDSUP to update the source address at the descriptor fetch time, otherwise
clear this bit.
5.3. Set XDMAC_CNDCx.NDDUP to update the destination address at the descriptor fetch time,
otherwise clear this bit.
5.4. Configure XDMAC_CNDCx.NDVIEW to define the length of the first descriptor.
6. Enable the End of Linked List interrupt by writing a ‘1’ to XDMAC_CIEx.LIE.
7. Enable channel x by writing a ‘1’ to XDMAC_GE.ENx. XDMAC_GS.STx is set by hardware.
8. Once completed, the DMA channel sets XDMAC_CISx.BIS (End of Block Interrupt Status bit) and generates
an interrupt. XDMAC_GS.STx is cleared by hardware. The software can either wait for an interrupt or poll the
channel status bit.
36.5.4.4 Disabling A Channel Before Transfer Completion
Under normal operation, the software enables a channel by writing a ‘1’ to XDMAC_GE.ENx, then the hardware
disables a channel on transfer completion by clearing bit XDMAC_GS.STx. To disable a channel, write a ‘1’ to bit
XDMAC_GD.DIx and poll the XDMAC_GS register.
36.6 Linked List Descriptor Operation
36.6.1 Linked List Descriptor View
36.6.1.1 Channel Next Descriptor View 0–3 Structures
Table 36-2. Channel Next Descriptor View 0–3 Structures
Channel Next Descriptor Offset Structure member Name
View 0 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA
DSCR_ADDR+0x04 Microblock Control Member MBR_UBC
DSCR_ADDR+0x08 Transfer Address Member MBR_TA
View 1 Structure DSCR_ADDR+0x00 Next Descriptor Address Member MBR_NDA
DSCR_ADDR+0x04 Microblock Control Member MBR_UBC
DSCR_ADDR+0x08 Source Address Member MBR_SA
DSCR_ADDR+0x0C Destination Address Member MBR_DA
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 461