Datasheet

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Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID)
I2SC0 Receive Right 49
I2SC1 Transmit Right 50
I2SC1 Receive Right 51
36.5 Functional Description
36.5.1 Basic Definitions
Source Peripheral: Slave device, memory mapped on the interconnection network, from where the XDMAC reads
data. The source peripheral teams up with a destination peripheral to form a channel. A data read operation is
scheduled when the peripheral transfer request is asserted.
Destination Peripheral: Slave device, memory mapped on the interconnection network, to which the XDMAC writes.
A write data operation is scheduled when the peripheral transfer request is asserted.
Channel: The data movement between source and destination creates a logical channel.
T
ransfer Type: The transfer is hardware-synchronized when it is paced by the peripheral hardware request,
otherwise the transfer is self-triggered (memory to memory transfer).
36.5.2 Transfer Hierarchy Diagram
XDMAC Master Transfer: The Master Transfer is composed of a linked list of blocks. The channel address, control
and configuration registers can be modified at the inter block boundary. The descriptor structure modifies the channel
registers conditionally. Interrupts can be generated on a per block basis or when the end of linked list event occurs.
XDMAC Block: An XDMAC block is composed of a programmable number of microblocks. The channel configuration
registers remain unchanged at the inter microblock boundary. The source and destination addresses are conditionally
updated with a programmable signed number.
XDMAC Microblock: The microblock is composed of a programmable number of data. The channel configuration
registers remain unchanged at the data boundary. The data address may be fixed (a FIFO location, a peripheral
transmit or receive register), incrementing (a memory-mapped area) by a programmable signed number.
XDMAC Burst and Incomplete Burst: In order to improve the overall performance when accessing dynamic
external memory, burst access is mandatory. Each data of the microblock is considered as a part of a memory burst.
The programmable burst value indicates the largest memory burst allowed on a per channel basis. When the
microblock length is not an integral multiple of the burst size, an incomplete burst is performed to read or write the
last trailing bytes.
XDMAC Chunk and Incomplete Chunk: When a peripheral synchronized transfer is activated, the microblock splits
into a number of data chunks. The chunk size is programmable. The larger the chunk is, the better the performance
is. When the transfer size is not a multiple of the chunk size, the last chunk may be incomplete.
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 458