Datasheet

36.3 Block Diagram
Figure 36-1. DMA Controller (XDMAC) Block Diagram
Status
Registers
Configuration
Registers
APB Interface
DMA
Interrupt
Dual Master AHB Interface
Request
Arbiter
Hardware
Request
Interface
Control and Data
Steering
Request
Pool
DMA
Read/Write
Datapath
AMBA AHB Layer
APB
Interface
DMA
Interrupt
Peripheral
Hardware
Requests
DMA
Channel
Data
FIFO
Destination
FSM
Source
FSM
DMA System
Controller
AMBA AHB Layer
36.4 DMA Controller Peripheral Connections
Table 36-1. Peripheral Hardware Requests
Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID)
HSMCI Transmit/Receive 0
SPI0 Transmit 1
SPI0 Receive 2
SPI1 Transmit 3
SPI1 Receive 4
QSPI Transmit 5
QSPI Receive 6
USART0 Transmit 7
USART0 Receive 8
USART1 Transmit 9
USART1 Receive 10
USART2 Transmit 11
USART2 Receive 12
SAM E70/S70/V70/V71 Family
DMA Controller (XDMAC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 456