Datasheet

36. DMA Controller (XDMAC)

36.1 Description

The DMA Controller (XDMAC) is a AHB-protocol central direct memory access controller. It performs peripheral data

transfer and memory move operations over one or two bus ports through the unidirectional communication channel.

Each channel is fully programmable and provides both peripheral or memory-to-memory transfers. The channel

features are configurable at implementation.

36.2 Embedded Characteristics

• 2 AHB Master Interfaces

•

24 DMA Channels

• 43 Hardware Requests

• 3.1 Kbytes Embedded FIFO

• Supports Peripheral-to-Memory, Memory-to-Peripheral, or Memory-to-Memory Transfer Operations

• Peripheral DMA Operation Runs on Bytes (8-bit), Half-Word (16-bit) and Word (32-bit)

• Memory DMA Operation Runs on Bytes (8 bit), Half-Word (16-bit) and Word (32 -bit)

• Supports Hardware and Software Initiated Transfers

• Supports Linked List Operations

• Supports Incrementing or Fixed Addressing Mode

• Supports Programmable Independent Data Striding for Source and Destination

• Supports Programmable Independent Microblock Striding for Source and Destination

• Configurable Priority Group and Arbitration Policy

• Programmable AHB Burst Length

• Configuration Interface Accessible through APB Interface

• XDMAC Architecture Includes Multiport FIFO

• Supports Multiple View Channel Descriptor

• Automatic Flush of Channel Trailing Bytes

• Automatic Coarse-Grain and Fine-Grain Clock Gating

• Hardware Acceleration of Memset Pattern

SAM E70/S70/V70/V71 Family

DMA Controller (XDMAC)

echnology Inc.

Datasheet

DS60001527D-page 455