Datasheet

Value Name Description
0
8_BIT 8-bit Data Bus
1
16_BIT 16-bit Data Bus
Bit 8 – BAT Byte Access T
ype
This field is used only if DBW defines a 16-bit data bus.
Value Name Description
0
BYTE_SELECT Byte select access type:
- W
rite operation is controlled using NCS, NWE, NBS0, NBS1.
- Read operation is controlled using NCS, NRD, NBS0, NBS1.
1
BYTE_WRITE Byte write access type:
- Write operation is controlled using NCS, NWR0, NWR1.
- Read operation is controlled using NCS and NRD.
Bits 5:4 – EXNW_MODE[1:0] NW
AIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse
phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration
must be programmed for the read and write controlling signal.
Value Name Description
0
DISABLED Disabled–The NWAIT input signal is ignored on the corresponding chip select.
1
Reserved
2
FROZEN
Frozen Mode–If asserted, the NWAIT signal freezes the current read or write cycle. After
deassertion, the read/write cycle is resumed from the point where it was stopped.
3
READY Ready Mode–The NWAIT signal indicates the availability of the external device at the end
of the pulse of the controlling read or write signal, to complete the access. If high, the
access normally completes. If low
, the access is extended until NWAIT returns high.
Bit 1 – WRITE_MODE W
rite Mode
Value Description
0
The write operation is controlled by the NCS signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of
NCS.
1
The write operation is controlled by the NWE signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of
NWE.
Bit 0 – READ_MODE Read Mode
Value Description
0
The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
1
The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 449