Datasheet

35.16.1.2 SMC Pulse Register
Name: SMC_PULSE[0..3]
Offset: 0x00
Reset: 0
Property: R/W
This register can only be written if the WPEN bit is cleared in the “SMC W
rite Protection Mode Register” .
Bit 31 30 29 28 27 26 25 24
NCS_RD_PULSE[6:0]
Access
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
NRD_PULSE[6:0]
Access
Reset 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NCS_WR_PULSE[6:0]
Access
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
NWE_PULSE[6:0]
Access
Reset 0 0 0 0 0 0 0
Bits 30:24 – NCS_RD_PULSE[6:0] NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In Page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
Bits 22:16 – NRD_PULSE[6:0]
NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In Page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the
page.
Bits 14:8 – NCS_WR_PULSE[6:0] NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
Bits 6:0 – NWE_PULSE[6:0] NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 446