Datasheet

35.16.1.1 SMC Setup Register
Name: SMC_SETUP[0..3]
Offset: 0x00
Reset: 0
Property: R/W
This register can only be written if the WPEN bit is cleared in the “SMC W
rite Protection Mode Register” .
Bit 31 30 29 28 27 26 25 24
NCS_RD_SETUP[5:0]
Access
Reset 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
NRD_SETUP[5:0]
Access
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
NCS_WR_SETUP[5:0]
Access
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
NWE_SETUP[5:0]
Access
Reset 0 0 0 0 0 0
Bits 29:24 – NCS_RD_SETUP[5:0] NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
Bits 21:16 – NRD_SETUP[5:0]
NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
Bits 13:8 – NCS_WR_SETUP[5:0] NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
Bits 5:0 – NWE_SETUP[5:0] NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 445