Datasheet

Figure 35-35. Page Mode Read Protocol (Address MSB and LSB are defined in T
able 35-7)
A[MSB]
NCS
MCK
NRD
D[7:0]
NCS_RD_PULSE NRD_PULSE
NRD_PULSE
tsatpa tsa
A[LSB]
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and
hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the
first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of
subsequent accesses within the page are defined using the NRD_PULSE parameter.
In Page mode, the programming of the read timings is described in the following table:
Table 35-8. Programming of Read Timings in Page Mode
Parameter Value Definition
READ_MODE 'x' No impact.
NCS_RD_SETUP 'x' No impact.
NCS_RD_PULSE t
pa
Access time of first access to the
page.
NRD_SETUP 'x' No impact.
NRD_PULSE t
sa
Access time of subsequent accesses
in the page.
NRD_CYCLE 'x' No impact.
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access
timing (t
pa
) and the NRD_PULSE for accesses to the page (t
sa
), even if the programmed value for t
pa
is shorter than
the programmed value for t
sa
.
35.15.2 Page Mode Restriction
The Page mode is not compatible with the use of the NWAIT signal. Using the Page mode and the NWAIT signal
may lead to unpredictable behavior.
35.15.3 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 35-7 are identical, then the current access lies in the
same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum
access time (t
sa
). The following figure illustrates access to an 8-bit memory device in Page mode, with 8-byte pages.
Access to D1 causes a page access with a long access time (t
pa
). Accesses to D3 and D7, though they are not
sequential accesses, only require a short access time (t
sa
).
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 442