Datasheet

Figure 35-34. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal
Mode to Slow Clock Mode
A [23:0]
NCS
1
MCK
NWE
1
1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
2
3
2
NORMAL MODE WRITEIDLE STATE
Reload Conf guration
Wait State
35.15 Asynchronous Page Mode
The SMC supports asynchronous burst reads in Page mode, provided that the Page mode is enabled
(SMC_MODE.PMEN =1). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32
bytes.
The page defines a set of consecutive bytes into memory
. A 4-byte page (resp. 8-, 16-, 32-byte page) is always
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memory, the LSB of address define the address of the data in the page as detailed in the
following table.
With Page mode memory devices, the first access to one page (t
pa
) takes longer than the subsequent accesses to
the page (t
sa
) as shown in Page Mode Read Protocol. When in Page mode, the SMC enables the user to define
different read timings for the first access within one page, and next accesses within the page.
Table 35-7. Page Address and Data Address within a Page
Page Size Page Address (see Note) Data Address in the Page
4 bytes A[23:2] A[1:0]
8 bytes A[23:3] A[2:0]
16 bytes A[23:4] A[3:0]
32 bytes A[23:5] A[4:0]
Note: “A” denotes the address bus of the memory device.
35.15.1 Protocol and Timings in Page Mode
The following figure shows the NRD and NCS timings in Page mode access.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 441