Datasheet

7. Power Considerations
7.1 Power Supplies
The following table defines the power supply rails of the SAM E70/S70/V70/V71 and the estimated power
consumption at typical voltage.
Table 7-1. Power Supplies
Name Associated Ground Powers
VDDCORE GND Core, embedded memories and
peripherals.
VDDIO GND Peripheral I/O lines (Input/Output
Buffers), backup part, 1 Kbytes of
backup SRAM, 32 kHz crystal
oscillator, oscillator pads. For USB
operations, VDDIO voltage range
must be between 3.0V and 3.6V.
VDDIN GND, GNDANA Voltage regulator input. Supplies also
the ADC, DAC and analog voltage
comparator.
VDDPLL GND, GNDPLL PLLA and the fast RC oscillator.
VDDPLLUSB GND, GNDPLLUSB UTMI PLL and the 3 to 20 MHz
oscillator.
VDDUTMII GNDUTMI USB transceiver interface. Must be
connected to VDDIO.
VDDUTMIC GNDUTMI USB transceiver core.
7.2 Power Constraints
The following power constraints are apply to SAM E70/S70/V70/V71 devices. Deviating from these constraints may
lead to unpredictable results.
•
VDDIN and VDDIO must have the same level
• VDDIN and VDDIO must always be higher than or equal to VDDCORE
• VDDCORE, VDDPLL and VDDUTMIC voltage levels must not vary by more than 0.6V
• For the USB to be operational, VDDUTMII, VDDPLLUSB, VDDIN and VDDIO must be higher than or equal to
3.0V
7.2.1 Powerup
VDDIO and VDDIN must rise simultaneously, prior to VDDCORE, VDDPLL and VDDUTMIC rising. This is respected
if VDDCORE, VDDPLL and VDDUTMIC are supplied by the embedded voltage regulator
.
If VDDCORE is powered by an external voltage regulator, VDDIO and VDDIN must reach their minimum operating
voltage before VDDCORE has reached VDDCORE
min
. The minimum slope for VDDCORE is defined by:
VDDCORE
min
 V
T+min
/ t
RESmin
If VDDCORE rises at the same time as VDDIO and VDDIN, the minimum and maximum rising slopes of VDDIO and
VDDIN must be respected. Refer to the section “DC Characteristics”.
In order to prevent any overcurrent at powerup, it is required that VREFP rises simultaneously with VDDIO and
VDDIN.
SAM E70/S70/V70/V71 Family
Power Considerations
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 44