Datasheet

Figure 35-31. NWAIT Latency
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
A
[23:0]
MCK
NRD
4 3
2 1 0 00
Read cycle
minimal pulse length
NWAIT latency
NWAIT
intenally synchronized
NWAIT signal
WAIT STATE
2 cycle resynchronization
35.14 Slow Clock Mode
The SMC is able to automatically apply a set of “Slow clock mode” read/write waveforms when an internal signal
driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate
(typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the Slow clock mode
waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate
waveforms at a very slow clock rate. When activated, the Slow clock mode is active on all chip selects.
35.14.1 Slow Clock Mode Waveforms
Figure 35-32 illustrates the read and write operations in Slow Clock mode. They are valid on all Chip Selects. T
able
35-6 indicates the value of read and write parameters in Slow Clock mode.
Figure 35-32. Read/Write Cycles in Slow Clock Mode
A[ 23:0]
NCS
1
MCK
NWE 1
1
NWE_CYCLE = 3
A [23:0]
MCK
NRD
NRD_CYCLE = 2
1
1
NCS
SLOW CLOCK MODE WRITE
SLOW CLOCK MODE READ
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 439