Datasheet

Figure 35-30. NWAIT Assertion in Read Access: Ready Mode (SMC_MODE.EXNW_MODE = 11)

EXNW_MODE = 11(Ready mode)

READ_MODE = 0 (NCS_controlled)

NRD_PULSE = 7

NCS_RD_PULSE =7

A[23:0]

MCK

NCS

NRD

456 3 2 0 0

456 3 2 11

Read cycle

Assertion is ignored

NWAIT

internally synchronized

NWAIT signal

Wait STATE

Assertion is ignored

35.13.4 NWAIT Latency and Read/Write Timings

There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT

signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this

latency plus the 2 cycles of resynchronization + one cycle. Otherwise, the SMC may enter the hold state of the

access without detecting the NW

AIT signal assertion. This is true in Frozen mode as well as in Ready mode. This is

illustrated in the following figure.

When SMC_MODE.EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read

and write controlling signal of at least:

Minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle

SAM E70/S70/V70/V71 Family

Static Memory Controller (SMC)

echnology Inc.

Datasheet

DS60001527D-page 438