Datasheet

If asserted, the SMC suspends the access as shown in Figure 35-29 and Figure 35-30. After deassertion, the access

is completed: the hold step of the access is performed.

This mode must be selected when the external device uses deassertion of the NW

AIT signal to indicate its ability to

complete the read or write operation.

If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling

read/write signal, it has no impact on the access length as shown in Figure 35-30.

Figure 35-29. NWAIT Assertion in Write Access: Ready Mode (SMC_MODE.EXNW_MODE = 11)

EXNW_MODE = 11 (Ready mode)

WRITE_MODE = 1 (NWE_controlled)

NWE_PULSE = 5

NCS_WR_PULSE = 7

[23:0]

MCK

NWE

NCS

4 3 2 1 0 00

456 3 2 1 1 1 0

Write cycle

D[7:0]

NWAIT

internally synchronized

NWAIT signal

Wait STATE

SAM E70/S70/V70/V71 Family

Static Memory Controller (SMC)

echnology Inc.

Datasheet

DS60001527D-page 437