Datasheet

Figure 35-27. Write Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[23:0]
MCK
NWE
NCS
4 3 2 1 1 1 01
456 3 2 2 2 2 1 0
Write cycle
D[7:0]
NWAIT
FROZEN STATE
internally synchronized
NWAIT signal
Figure 35-28. Read Access with NWAIT Assertion in Frozen Mode (SMC_MODE.EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
A
[23:0]
MCK
NCS
NRD
1 0
4 3
4 3
2
5 5 5
2 2 0
2 1 0
2 1 0
1
Read cycle
Assertion is ignored
NWAIT
internally synchronized
NWAIT signal
FROZEN STATE
35.13.3 Ready Mode
In Ready mode (SMC_MODE.EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the
access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the
pulse phase, the resynchronized NW
AIT signal is examined.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 436