Datasheet

Figure 35-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
TDF_CYCLES = 5
TDF_CYCLES = 5
TDF_MODE = 0
(optimization disabled)
A
[23:0]
read1 cycle
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[7:0]
read1 hold = 1
write2 cycle
write2 setup = 1
4 TDF WAIT STATES
35.13 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The
SMC_MODE.EXNW_MODE field on the corresponding chip select must be set either to “10” (Frozen mode) or “11”
(Ready mode). When SMC_MODE.EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the
corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write
controlling signal, depending on the Read and Write modes of the corresponding chip select.
35.13.1 Restriction
When SMC_MODE.EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write
controlling signal. For that reason, the NWAIT signal cannot be used in Page mode (35.15 Asynchronous Page
Mode), or in Slow clock mode (”Slow Clock Mode”).
The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then
NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the
NWAIT signal outside the expected period has no impact on SMC behavior.
35.13.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the
SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the
resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point
where it was stopped. See Figure 35-27. This mode must be selected when the external device uses the NWAIT
signal to delay the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 35-28.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 435