Datasheet

Figure 35-20. Early Read Wait State: NWE-controlled write with no hold followed by a read with one set-
up cycle
A [25:2]
write cycle
(WRITE_MODE = 1)
Early Read
wait state
MCK
NRD
internal write controlling signal
external write controlling signal
(NWE)
D[7:0]
read cycle
no hold
read setup = 1
(READ_MODE = 0 or READ_MODE = 1)
35.11.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state
before starting the next access. This “reload user configuration wait state” is used by the SMC to load the new set of
parameters to apply to next accesses.
The reload configuration wait state is not applied in addition to the chip select wait state. If accesses before and after
re-programming the user interface are made to dif
ferent devices (chip selects), then one single chip select wait state
is applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a reload
configuration wait state is inserted, even if the change does not concern the current chip select.
35.11.3.1 User Procedure
To insert a reload configuration wait state, the SMC detects a write access to any SMC_MODE register of the user
interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user
interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode
parameters.
The user must not change the configuration parameters of an SMC chip select (Setup, Pulse, Cycle, Mode) if
accesses are performed on this CS during the modification. Any change of the chip select parameters, while fetching
the code from a memory connected on this CS, may lead to unpredictable behavior. The instructions used to modify
the parameters of an SMC chip select can be executed from the internal RAM or from a memory connected to
another CS.
35.11.3.2 Slow Clock Mode Transition
A reload configuration wait state is also inserted when the Slow Clock mode is entered or exited, after the end of the
current transfer (see ”Slow Clock Mode”).
35.11.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be
inserted. See Figure 12-1.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 431