Datasheet

• if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 35-18).
•
in NCS Write controlled mode (SMC_MODE.WRITE_MODE = 0), if there is no hold timing on the NCS signal
and the NCS_RD_SETUP parameter is set to 0, regardless of the Read mode (Figure 35-19). The write
operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not
complete properly.
• in NWE controlled mode (SMC_MODE.WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the
feedback of the write control signal is used to control address, data, and chip select lines. If the external write
control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and
address, data and control signals are maintained one more cycle. See Figure 35-20.
Figure 35-18. Early Read Wait State: Write with No Hold Followed by Read with No Setup
write cycle
Early Read
wait state
MCK
NRD
NWE
read cycle
no setup
no hold
D[7:0]
A[23:0]
Figure 35-19. Early Read Wait State: NCS-controlled write with no hold followed by a read with no NCS
setup
write cycle
(WRITE_MODE = 0)
Early Read
wait state
MCK
NRD
NCS
read cycle
no setup
no hold
D[7:0]
A[23:0]
(READ_MODE = 0 or READ_MODE = 1)
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 430