Datasheet

The scrambling/unscrambling function can be enabled or disabled by configuring the CSxSE bits in the SMC Off-Chip
Memory Scrambling Register (SMC_OCMS).
When multiple chip selects are handled, the scrambling function per chip select is configurable using the CSxSE bits
in the SMC_OCMS register
.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2 plus a random
value depending on device processing characteristics. These key registers cannot be read. They can be written once
after a system reset.
The scrambling user key or the seed for key generation must be securely stored in a reliable non-volatile memory in
order to recover data from the off-chip memory. Any data scrambled with a given key cannot be recovered if the key
is lost.
35.11 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or
operation conflict.
35.11.1 Chip Select Wait States
The SMC always inserts an idle cycle between two transfers on separate Chip Selects. This idle cycle ensures that
there is no bus contention between the deactivation of one device and the activation of the next one.
During Chip Select W
ait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.
The following figure illustrates a Chip Select Wait state between access on Chip Select 0 and Chip Select 2.
Figure 35-17. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
A[23:0]
NCS0
NRD_CYCLE
Chip Select
Wait State
NWE_CYCLE
MCK
NCS2
NRD
NWE
D[7:0]
Read to Write
Wait State
35.11.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the
write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip
select wait state. The early read cycle thus only occurs between a write and read access to the same memory device
(same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 429