Datasheet

• NWE_CYCLE
The following table shows how the timing parameters are coded and their permitted range.
T
able 35-4. Coding and Range of Timing Parameters
Coded Value Number of Bits Effective Value Permitted Range
Coded Value Effective Value
setup [5:0] 6 128 × setup[5] + setup[4:0] 0 ≤ 31 0 ≤ 128+31
pulse [6:0] 7 256 × pulse[6] + pulse[5:0] 0 ≤ 63 0 ≤ 256+63
cycle [8:0] 9 256 × cycle[8:7] + cycle[6:0] 0 ≤ 127 0 ≤ 256+127
0 ≤ 512+127
0 ≤ 768+127
35.9.7 Reset Values of Timing Parameters
The following table provides the default value of timing parameters at reset.
T
able 35-5. Reset Values of Timing Parameters
Parameter Reset Value Definition
SMC_SETUP 0x01010101 All setup timings are set to 1.
SMC_PULSE 0x01010101 All pulse timings are set to 1.
SMC_CYCLE 0x00030003 The read and write operations continue for 3 Master Clock cycles and provide one
hold cycle.
WRITE_MODE 1 Write is controlled with NWE.
READ_MODE 1 Read is controlled with NRD.
35.9.8 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE
parameters is larger than the corresponding CYCLE parameter
, this leads to unpredictable behavior of the SMC.
• For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory
interface because of the propagation delay of theses signals through external logic and pads. If positive setup
and hold values must be verified, then it is strictly recommended to program non-null values so as to cover
possible skews between address, NCS and NRD signals.
• For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal
after the rising edge of NWE. This is true for SMC_MODE.WRITE_MODE = 1 only. See ”Early Read Wait State”.
• For read and write operations:
A null value for pulse parameters is forbidden and may lead to unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
35.10 Scrambling/Unscrambling Function
The external data bus can be scrambled to protect intellectual property data located in off-chip memories by means
of data analysis at the package pin level of either the microcontroller or the memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 428