Datasheet

35.8.1.2 NOR Flash
Hardware Configuration
Figure 35-8. NOR Flash
A21
A1
A0
A2
A3
A4
A5
A6
A7
A8
A15
A9
A12
A13
A11
A10
A14
A16
D6
D0
D3
D4
D2
D1
D5
D7
A17
A20
A18
A19
D[0..7]
A
[0..21]
NRST
NWE
NCS0
NRD
3V3
3V3
C2
100NF
C2
100NF
C1
100NF
C1
100NF
U1U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A21
A20
A19
WE
RESET
WP
OE
CE
VPP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCCQ
VSS
VSS
VCC
Software Configuration
Configure the SMC CS0 Setup, Pulse, Cycle, and Mode, depending on Flash timings and system bus frequency
.
35.9 Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS1) always have the
same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the
byte write lines (NWR0 to NWR1) in byte write access type. NWR0 to NWR1 have the same timings and protocol as
NWE. If D[15:8] are used, they have the same timing as D[7:0]. In the same way, NCS represents one of the
NCS[0..3] chip select lines.
35.9.1 Read Waveforms
The read cycle is shown in the following figure.
The read cycle starts with the address setting on the memory address bus.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 421