Datasheet

Table 35-3. SMC Multiplexed Signal Translation
Device Type Signal Name
16-bit Bus 8-bit Bus
1 x 16-bit 2 x 8-bit 1 x 8-bit
Byte Access Type (BAT) Byte Select Byte Write –
NBS0_A0 NBS0 – A0
NWE_NWR0 NWE NWR0 NWE
NBS1_NWR1 NBS1 NWR1 –
A1 A1 A1 A1
35.7.3 NAND Flash Support
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the SMC. Configuration is done via
the SMC_NFCSx field in the
CCFG_SMCNFCS register in the Bus Matrix. For details on this register, refer to the section “Bus Matrix (MATRIX)”
of this datasheet. The external NAND Flash device is accessed via the address space reserved for the chip select
programmed.
The user can connect up to four NAND Flash devices with separate chip selects.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer address
fails to lie in the NCSx programmed address space.
Figure 35-5. NAND Flash Signal Multiplexing on SMC Pins
SMC
NRD
NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx
NANDW
E
NANDO
E
Note:
1. NCSx is active when CCFG_SMCNFCS.SMC_NFCSx=1.
Note: 2. When the NAND Flash logic is activated, (SMC_NFCSx=1), the NWE pin can be used only in Peripheral
mode (NWE function). If the NWE function is not used for other external memories (SRAM, LCD), it must be
configured in one of the following modes:
PIO input with pull-up enabled (default state after reset)
and PIO output set at level 1.
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits
A22 and A21of the address bus. Any bit of the address bus can also be used for this purpose. The command,
address or data words on the data bus of the NAND Flash device use their own addresses within the NCSx address
space (configured in the register CCFG_SMCNFCS in the Bus Matrixe). The chip enable (CE) signal of the device
and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NAND
Flash chip select is not selected, preventing the device from returning to Standby mode. The NANDCS output signal
should be used in accordance with the external NAND Flash device type.
Two types of CE behavior exist depending on the NAND Flash device:
• Standard NAND Flash devices require that the CE pin remains asserted low continuously during the read busy
period to prevent the device from returning to Standby mode. Since the SMC asserts the NCSx signal high, it is
necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to hold it low during the busy
period preceding data read out.
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 418