Datasheet

Figure 35-1. Memory Connections for Four External Devices
NRD
NWE
A[23:0]
D[15:0]
16 or 8
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[23:0]
D[15:0] or D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS[0] - NCS[3]
SMC
24
35.7 Connection to External Devices
35.7.1 Data Bus Width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the bit DBW in the
Mode register (SMC_MODE) for the corresponding chip select.
Figure 35-2 shows how to connect a 512-Kbyte × 8-bit memory on NCS2.
Figure 35-3 shows how to connect a 512-
Kbyte × 16-bit memory on NCS2.
Figure 35-2. Memory Connection for an 8-bit Data Bus
SMC
A1
NWE
NRD
NCS[2]
A1
Write Enable
Output Enable
Memory Enable
D[7:0] D[7:0]
A[18:2]
A[18:2]
A0
A0
Figure 35-3. Memory Connection for a 16-bit Data Bus
SMC
NBS0
NWE
NRD
NCS[2]
Low Byte Enable
Write Enable
Output Enable
Memory Enable
NBS1 High Byte Enable
D[15:0] D[15:0]
A[19:2]
A[18:1]
A[0]A1
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 416