Datasheet

...........continued
Name Description Type Active Level
NWAIT External Wait Signal Input Low
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NANDALE NAND Flash Address Latch Enable Output –
NANDCLE NAND Flash Command Latch Enable Output –
35.4 Multiplexed Signals
Table 35-2. Static Memory Controller (SMC) Multiplexed Signals
Multiplexed Signals Related Function
NWR0 NWE Byte-write or Byte-select access.
See ”Byte W
rite Access” and ”Byte Select Access”
A0 NBS0 8-bit or 16-bit data bus. See ”Data Bus Width”
NWR1 NBS1 Byte-write or Byte-select access. See ”Byte Write Access” and ”Byte Select Access”
A22 NANDCLE NAND Flash Command Latch Enable
A21 NANDALE NAND Flash Address Latch Enable
35.5 Product Dependencies
35.5.1 I/O Lines
The pins used for interfacing the SMC are multiplexed with the PIO lines. The programmer must first program the PIO
controller to assign the SMC pins to their peripheral function. If I/O lines of the SMC are not used by the application,
they can be used for other purposes by the PIO Controller
.
35.5.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SMC clock.
35.6 External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and appears
to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page
(see the following figure).
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 415