Datasheet

35. Static Memory Controller (SMC)
35.1 Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices
and the ARM-based microcontroller
. The Static Memory Controller (SMC) is part of the EBI.
The SMC handles several types of external memory and peripheral devices, such as SRAM, PSRAM, PROM,
EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
The SMC generates the signals that control the access to the external memory devices or peripheral devices. It has 4
chip selects, a 24-bit address bus, and a configurable 8 or 16-bit data bus. Separate read and write control signals
allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with
an automatic Slow clock mode. In Slow clock mode, it switches from user-programmed waveforms to slow-rate
specific waveforms on read and write signals. The SMC supports asynchronous burst read in Page mode access for
page sizes up to 32 bytes.
The external data bus can be scrambled/unscrambled by means of user keys.
35.2 Embedded Characteristics
• Four Chip Selects Available
• 16-Mbyte Address Space per Chip Select
• 8-bit or 16-bit Data Bus
• Zero Wait State Scrambling/Unscrambling Function with User Key
• Word, Halfword, Byte Transfers
• Byte Write or Byte Select Lines
• Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
• Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
• Programmable Data Float Time per Chip Select
• External Wait Request
• Automatic Switch to Slow Clock Mode
• Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
• Register Write Protection
35.3 I/O Lines Description
Table 35-1. I/O Line Description
Name Description Type Active Level
NCS[3:0] Static Memory Controller Chip Select Lines Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low
A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low
A[23:1] Address Bus Output –
D[15:0] Data Bus I/O –
SAM E70/S70/V70/V71 Family
Static Memory Controller (SMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 414