Datasheet

34.7.13 SDRAMC OCMS KEY2 Register
Name: SDRAMC_OCMS_KEY2
Offset: 0x34
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
KEY2[31:24]
Access
W W W W W W W W
Reset – – – – – – – –
Bit 23 22 21 20 19 18 17 16
KEY2[23:16]
Access
W W W W W W W W
Reset – – – – – – – –
Bit 15 14 13 12 11 10 9 8
KEY2[15:8]
Access
W W W W W W W W
Reset – – – – – – – –
Bit 7 6 5 4 3 2 1 0
KEY2[7:0]
Access
W W W W W W W W
Reset – – – – – – – –
Bits 31:0 – KEY2[31:0] Of
f-chip Memory Scrambling (OCMS) Key Part 2
When off-chip memory scrambling is enabled, the data scrambling depends on KEY1 and KEY2 values.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 413