Datasheet

34.7.10 SDRAMC Configuration Register 1
Name: SDRAMC_CFR1
Offset: 0x28
Reset: 0x00000002
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
UNAL
Access
R/W
Reset 0
Bit 7 6 5 4 3 2 1 0
TMRD[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 1 0
Bit 8 – UNAL Support Unaligned Access
This mode is enabled with masters which have an AXI interface.
Value Name Description
0
UNSUPPORTED Unaligned access is not supported.
1
SUPPORTED Unaligned access is supported.
Bits 3:0 – TMRD[3:0] Load Mode Register Command to Active or Refresh Command
Reset value is 2 cycles.
This field defines the delay between a “Load Mode Register” command and an active or refresh command in number
of cycles. Number of cycles is between 0 and 15.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 410