Datasheet

34.7.9 SDRAMC Memory Device Register
Name: SDRAMC_MDR
Offset: 0x24
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
MD[1:0]
Access
R/W R/W
Reset 0 0
Bits 1:0 – MD[1:0] Memory Device T
ype
Value Name Description
0
SDRAM SDRAM
1
LPSDRAM Low-power SDRAM
2
– Reserved
3
– Reserved
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 409