Datasheet

34.7.8 SDRAMC Interrupt Status Register
Name: SDRAMC_ISR
Offset: 0x20
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RES
Access
R
Reset 0
Bit 0 – RES Refresh Error Status (cleared on read)
Value Description
0
No refresh error has been detected since the register was last read.
1
A refresh error has been detected since the register was last read.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 408