Datasheet

34.7.6 SDRAMC Interrupt Disable Register
Name: SDRAMC_IDR
Offset: 0x18
Property: Write-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
RES
Access
W
Reset
Bit 0 – RES Refresh Error Interrupt Disable
Value Description
0
No effect.
1
Disables the refresh error interrupt.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 406