Datasheet

34.7.4 SDRAMC Low-Power Register
Name: SDRAMC_LPR
Offset: 0x10
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
TIMEOUT[1:0] DS[1:0] TCSR[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PASR[2:0] LPCB[1:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bits 13:12 – TIMEOUT[1:0] T
ime to Define When Low-power Mode Is Enabled
Value Name Description
0
LP_LAST_XFER The SDRAMC activates the SDRAM Low-power mode immediately after the
end of the last transfer
.
1
LP_LAST_XFER_64 The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the
end of the last transfer.
2
LP_LAST_XFER_128 The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after
the end of the last transfer.
3
Reserved
Bits 11:10 – DS[1:0] Drive Strength (only for low-power SDRAM)
DS is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter
must be set according to the SDRAM device specification.
After initialization, as soon as the DS field is modified and Self-refresh mode is activated, the Extended Mode
Register is accessed automatically and DS bits are updated before entry in Self-refresh mode. This feature is not
supported when SDRAMC shares an external bus with another controller
.
Bits 9:8 – TCSR[1:0] Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR is transmitted to the SDRAM during initialization to set the refresh interval during Self-refresh mode depending
on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
After initialization, as soon as the TCSR field is modified and Self-refresh mode is activated, the Extended Mode
Register is accessed automatically and TCSR bits are updated before entry in Self-refresh mode. This feature is not
supported when SDRAMC shares an external bus with another controller.
Bits 6:4 – PASR[2:0] Partial Array Self-refresh (only for low-power SDRAM)
PASR is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of
the SDRAM array are enabled. Disabled banks are not refreshed in Self-refresh mode. This parameter must be set
according to the SDRAM device specification.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 403