Datasheet

34.7.3 SDRAMC Configuration Register
Name: SDRAMC_CR
Offset: 0x08
Reset: 0x852372C0
Property: Read/Write
WARNING
Bit 7 (DBW) must always be set when programming the SDRAMC_CR.
Bit 31 30 29 28 27 26 25 24
TXSR[3:0] TRAS[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 0 0 0 0 1 0 1
Bit 23 22 21 20 19 18 17 16
TRCD[3:0] TRP[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 1 0 0 0 1 1
Bit 15 14 13 12 11 10 9 8
TRC_TRFC[3:0] TWR[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 1 1 1 0 0 1 0
Bit 7 6 5 4 3 2 1 0
DBW CAS[1:0] NB NR[1:0] NC[1:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 1 1 0 0 0 0 0 0
Bits 31:28 – TXSR[3:0] Exit Self-Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles
is between 0 and 15.
Bits 27:24 – TRAS[3:0]
Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number
of cycles is between 0 and 15.
Bits 23:20 – TRCD[3:0] Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate Command and a Read/Write Command in number of cycles.
Number of cycles is between 0 and 15.
Bits 19:16 – TRP[3:0] Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge Command and another Command in number of cycles. Number of
cycles is between 0 and 15.
Bits 15:12 – TRC_TRFC[3:0] Row Cycle Delay and Row Refresh Cycle
Reset value is seven cycles.
This field defines two timings:
• the delay (t
RFC
) between two Refresh commands and between a Refresh command and an Activate command
• the delay (t
RC
) between two Active commands in number of cycles.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 401