Datasheet

34.7.1 SDRAMC Mode Register
Name: SDRAMC_MR
Offset: 0x00
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
MODE[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bits 2:0 – MODE[2:0] SDRAMC Command Mode
This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
Value Name Description
0
NORMAL Normal mode. Any access to the SDRAM is decoded normally. To activate
this mode, the command must be followed by a write to the SDRAM.
1
NOP The SDRAMC issues a NOP command when the SDRAM device is
accessed regardless of the cycle. T
o activate this mode, the command
must be followed by a write to the SDRAM.
2
ALLBANKS_PRECHARGE The SDRAMC issues an “All Banks Precharge” command when the
SDRAM device is accessed regardless of the cycle. To activate this mode,
the command must be followed by a write to the SDRAM.
3
LOAD_MODEREG The SDRAMC issues a “Load Mode Register” command when the
SDRAM device is accessed regardless of the cycle. To activate this mode,
the command must be followed by a write to the SDRAM.
4
AUTO_REFRESH The SDRAMC issues an “Autorefresh” Command when the SDRAM
device is accessed regardless of the cycle. Previously, an “All Banks
Precharge” command must be issued. To activate this mode, the
command must be followed by a write to the SDRAM.
5
EXT_LOAD_MODEREG The SDRAMC issues an “Extended Load Mode Register” command when
the SDRAM device is accessed regardless of the cycle. To activate this
mode, the “Extended Load Mode Register” command must be followed by
a write to the SDRAM. The write in the SDRAM must be done in the
appropriate bank; most low-power SDRAM devices use the bank 1.
6
DEEP_POWERDOWN Deep Powerdown mode. Enters Deep Powerdown mode.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 399