Datasheet

34.7 Register Summary
Offset Name Bit Pos.
0x00 SDRAMC_MR
7:0 MODE[2:0]
15:8
23:16
31:24
0x04 SDRAMC_TR
7:0 COUNT[7:0]
15:8 COUNT[11:8]
23:16
31:24
0x08 SDRAMC_CR
7:0 DBW CAS[1:0] NB NR[1:0] NC[1:0]
15:8 TRC_TRFC[3:0] TWR[3:0]
23:16 TRCD[3:0] TRP[3:0]
31:24 TXSR[3:0] TRAS[3:0]
0x0C
...
0x0F
Reserved
0x10 SDRAMC_LPR
7:0 PASR[2:0] LPCB[1:0]
15:8 TIMEOUT[1:0] DS[1:0] TCSR[1:0]
23:16
31:24
0x14 SDRAMC_IER
7:0 RES
15:8
23:16
31:24
0x18 SDRAMC_IDR
7:0 RES
15:8
23:16
31:24
0x1C SDRAMC_IMR
7:0 RES
15:8
23:16
31:24
0x20 SDRAMC_ISR
7:0 RES
15:8
23:16
31:24
0x24 SDRAMC_MDR
7:0 MD[1:0]
15:8
23:16
31:24
0x28 SDRAMC_CFR1
7:0 TMRD[3:0]
15:8 UNAL
23:16
31:24
0x2C SDRAMC_OCMS
7:0 SDR_SE
15:8
23:16
31:24
0x30
SDRAMC_OCMS_K
EY1
7:0 KEY1[7:0]
15:8 KEY1[15:8]
23:16 KEY1[23:16]
31:24 KEY1[31:24]
0x34
SDRAMC_OCMS_K
EY2
7:0 KEY2[7:0]
15:8 KEY2[15:8]
23:16 KEY2[23:16]
31:24 KEY2[31:24]
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 398