Datasheet

A refresh error interrupt is generated when the previous autorefresh command did not perform. It is acknowledged by
reading the Interrupt Status register (SDRAMC_ISR).
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However
, if
the processor tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait
signal. Refer to the following figure.
Figure 34-5. Refresh Cycle Followed by a Read Access
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
DATA
(input)
t
RP
SDWE
Dnb
Dnc
Dnd
col c col d
CAS
Row m
col a
t
RFC
t
RCD
Dma
Row n
34.6.5 Power Management
Three low-power modes are available:
•
Self-refresh mode: The SDRAM executes its own Autorefresh cycle without control of the SDRAMC. Current
drained by the SDRAM is very low.
• Powerdown mode: Autorefresh cycles are controlled by the SDRAMC. Between autorefresh cycles, the SDRAM
is in powerdown. Current drained in Powerdown mode is higher than in Self-refresh Mode.
• Deep Powerdown mode (only available with Mobile SDRAM): The SDRAM contents are lost, but the SDRAM
does not drain any current.
The SDRAMC activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay
the entry in Self-refresh and Powerdown modes after the last access by programming a timeout value in the
SDRAMC_LPR.
34.6.5.1 Self-refresh Mode
This mode is selected by configuring SDRAMC_LPR.LPCB to 1. In Self-refresh mode, the SDRAM device retains
data without external clocking and provides its own internal clocking, thus performing its own autorefresh cycles. All
the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM
device is selected, the SDRAMC provides a sequence of commands and exits Self-refresh mode.
Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one-quarter or a half quarter or all banks of the
SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated
Self-Refresh (TCSR), Partial Array Self-Refresh (PASR) and Drive Strength (DS) must be set in the SDRAMC_LPR
and transmitted to the low-power SDRAM during initialization.
After initialization, as soon as the PASR/DS/TCSR fields are modified and Self-refresh mode is activated, the
Extended Mode register is accessed automatically and the PASR/DS/TCSR bits are updated before entry into Self-
refresh mode. This feature is not supported when SDRAMC shares an external bus with another controller.
The SDRAM device must remain in Self-refresh mode for a minimum period of t
RAS
and may remain in Self-refresh
mode for an indefinite period. Refer to the following figure.
Note: Some SDRAM providers impose some cycles of burst autorefresh immediately before self-refresh entry and
immediately after self-refresh exit. For example, a SDRAM with 4096 rows will impose 4096 cycles of burst
autorefresh. This constraint is not supported.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 395