Datasheet

Figure 34-1. SDRAM Device Initialization Sequence
SDCK
SDRAMC_A[9:0]
A10
S
DRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
NBS
Inputs stable for
200 μs
Precharge All Banks 1st Autorefresh 8th Autorefresh MRS Command Valid Command
SDCKE
t
RP
t
RFC
t
MRD
34.5.2 I/O Lines
The pins used for interfacing the SDRAMC may be multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the SDRAMC pins to their peripheral function. If I/O lines of the SDRAMC are
not used by the application, they can be used for other purposes by the PIO Controller
.
34.5.3 Power Management
The SDRAMC may be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the SDRAMC clock.
The SDRAM clock on pin SDCK is output as soon as the first access to the SDRAM is made during the initialization
phase. T
o stop the SDRAM clock signal, the SDRAMC_LPR must be programmed with the self-refresh command.
34.5.4 Interrupt Sources
The SDRAMC interrupt (Refresh Error notification) is connected to the memory controller. This interrupt may be
ORed with other system peripheral interrupt lines and is finally provided as the system interrupt source (Source 1) to
the interrupt controller
.
Using the SDRAMC interrupt requires the interrupt controller to be programmed first.
34.6 Functional Description
34.6.1 SDRAM Controller Write Cycle
The SDRAMC allows burst access or single access. In both cases, the SDRAMC keeps track of the active row in
each bank, thus maximizing performance. T
o initiate a burst access, the SDRAMC uses the transfer type signal
provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM
device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or
if the next access is in another row, then the SDRAMC generates a precharge command, activates the new row and
initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between
precharge and active commands (t
RP
), and between active and write commands (t
RCD
). For definition of these timing
parameters, refer to the SDRAMC Configuration Register. Refer to the following figure.
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 392