Datasheet

...........continued
Name Description Type Active Level
RAS Row Signal Output Low
CAS Column Signal Output Low
SDWE SDRAM Write Enable Output Low
NBS[1:0] Data Mask Enable Signals Output Low
SDRAMC_A[12:0] Address Bus Output –
D[15:0] Data Bus I/O –
34.4 Software Interface/SDRAM Organization, Address Mapping
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows mapping different
memory types according to the values set in the Configuration register (SDRAMC_CR).
The SDRAMC makes the SDRAM device access protocol transparent to the user
. The following tables illustrate the
SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are
illustrated.
34.4.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width
Table 34-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[10:0] Column[7:0] M0
Bk[1:0] Row[10:0] Column[8:0] M0
Bk[1:0] Row[10:0] Column[9:0] M0
Bk[1:0] Row[10:0] Column[10:0] M0
Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0.
T
able 34-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[11:0] Column[7:0] M0
Bk[1:0] Row[11:0] Column[8:0] M0
Bk[1:0] Row[11:0] Column[9:0] M0
Bk[1:0] Row[11:0] Column[10:0] M0
Note: M0 is the byte address inside a 16-bit half-word and Bk[1] = BA1, Bk[0] = BA0.
T
able 34-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Row[12:0] Column[7:0] M0
Bk[1:0] Row[12:0] Column[8:0] M0
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 390