Datasheet

34. SDRAM Controller (SDRAMC)
34.1 Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to external
16-bit DRAM devices. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to
2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active row in each bank, thus
maximizing SDRAM performance, for example, the application may be placed in one bank and data in the other
banks. For optimized performance, it is advisable to avoid accessing dif
ferent rows in the same bank.
The SDRAMC supports a CAS latency of 2 or 3 and optimizes the read access depending on the frequency.
The available different modes, such as Self-refresh, Powerdown and Deep Powerdown modes, minimizes the power
consumption on the SDRAM device.
34.2 Embedded Characteristics
• Numerous Configurations Supported
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
• Programming Facilities
– Word, half-word, byte access
– Automatic Page break when memory boundary has been reached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
• Energy-Saving Capabilities
– Self-refresh, Powerdown and Deep Power modes Supported
– Supports mobile SDRAM devices
• Error Detection
– Refresh error interrupt
• SDRAM Power-up Initialization by Software
• CAS Latency of 2, 3 Supported
• Auto Precharge Command Not Used
• Zero Wait State Scrambling/Unscrambling Function with User Key
34.3 Signal Description
Table 34-1. Signal Description
Name Description Type Active Level
SDCK SDRAM Clock Output –
SDCKE SDRAM Clock Enable Output High
SDCS SDRAMC Chip Select Output Low
BA[1:0] Bank Select Signals Output –
SAM E70/S70/V70/V71 Family
SDRAM Controller (SDRAMC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 389