Datasheet

...........continued
Name Function Type Active Level
SMC
NCS0–EBI_NCS3 Chip Select Lines Output Low
NWR0–NWR1 Write Signals Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0–NBS1 Byte Mask Signals Output Low
EBI for NAND Flash Support
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
SDRAM Controller
SDCK (see Note) SDR-SDRAM Clock Output
SDCKE SDR-SDRAM Clock Enable Output High
SDCS SDR-SDRAM Controller Chip Select Line Output Low
BA0–1 Bank Select Output
SDWE SDR-SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
SDA10 SDRAM Address 10 Line Output
Note: SDCK is the MCK clock for EBI, SDRAM Controller and SMC interfaces.
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at
the moment.
The following table details the connections between the two Memory Controllers and the EBI pins.
T
able 33-2. EBI Pins and Memory Controllers I/O Lines Connections
EBIx Pins SDRAM I/O Lines SMC I/O Lines
NWR1/NBS1 NBS1 NWR1
A0/NBS0 NBS0 SMC_A0
A1 Not Supported SMC_A1
A[11:2] SDRAMC_A[9:0] SMC_A[11:2]
SDA10 SDRAMC_A10 Not Supported
A12 Not Supported SMC_A12
A[15:13] SDRAMC_A[13:11] SMC_A[15:13]
A[25:16] Not Supported SMC_A[25:16]
D[15:0] D[15:0] D[15:0]
SAM E70/S70/V70/V71 Family
External Bus Interface
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 384