Datasheet

33.3 EBI Block Diagram
Figure 33-1. Organization of the External Bus Interface
External Bus Interface
D[15:0]
A[15:2], A19
PIO
MUX
Logic
User Interface
Chip Select
Assignor
Static
Memory
Controller
SDR-SDRAM
Controller
Bus Matrix
APB
AHB
Address Decoders
A16/BA0
A0/NBS0
A1
A17/BA1
NCS0
NRD
NCS1/SDCS
NWR0/NWE
NWR1/NBS1
SDCK, SDCKE
DQM[1:0]
RAS, CAS
SDWE, SDA10
A[23:20]
NCS2
NWAIT
NANDOE
NANDWE
NAND Flash
Logic
A21/NANDALE
A22/NANDCLE
NCS3/NANDCS
A18
33.4 I/O Lines Description
Table 33-1. EBI I/O Lines Description
Name Function Type Active Level
EBI
D0–D15 Data Bus I/O
A0–A23 Address Bus Output
NWAIT External Wait Signal Input Low
SAM E70/S70/V70/V71 Family
External Bus Interface
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 383