Datasheet

32.6.1.54 PIO Parallel Capture Interrupt Status Register
Name: PIO_PCISR
Offset: 0x0160
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
OVRE DRDY
Access
Reset 0 0
Bit 1 – OVRE Parallel Capture Mode Overrun Error
The OVRE flag is automatically reset when this register is read or when the Parallel Capture mode is disabled.
Value Description
0
No overrun error occurred since the last read of this register.
1
At least one overrun error occurred since the last read of this register.
Bit 0 – DRDY Parallel Capture Mode Data Ready
The DRDY flag is automatically reset when PIO_PCRHR is read or when the Parallel Capture mode is disabled.
Value Description
0
No new data is ready to be read since the last read of PIO_PCRHR.
1
A new data is ready to be read since the last read of PIO_PCRHR.
SAM E70/S70/V70/V71 Family
Parallel Input/Output Controller (PIO)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 380